Methods and systems to measure a signal on an integrated circuit die

ABSTRACT

Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement ent circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.

CLAIM OF PRIORITY

This application is a continuation application, and claims priority, of U.S. patent application Ser. No. 12/978,456 filed Dec. 24, 2010, to be issued as U.S. Pat. No. 8,860,455 on Oct. 14, 2014, and is incorporated by reference in its entirety.

BACKGROUND

Automated and semi-automated techniques have been developed to test integrated circuits (ICs). Causes of faults or errors encountered during testing are, however, notoriously difficult to trace.

For example, an IC may receive an analog system reference voltage, and may include one or more voltage dividers to generate one or more additional analog voltages from the system reference voltage. Other circuitry within the IC may utilize one or more of the analog voltages as reference voltages, bandgap reference voltages, and/or bias voltages. An analog voltage may encounter a voltage or IR drop due to distance from a driver or buffer circuit, loading effects of associated circuitry, and/or fabrication variations that may affect characteristics of the die itself. An IR drop may impact operation of the IC in one or more of a variety of ways, including slowed response times and loss of functionality, which may be detected as an error or fault during testing of the IC.

To trace or debug the source of the error or fault, on-die analog signals may be measured with an off-die measurement device, such as an oscilloscope or volt meter. Conventionally, multiple on-die signals are multiplexed to one or more off-die accessible pads through analog multiplexers, often through relatively long and circuitous signal routes, which may itself introduce IR drops, capacitive loads, and/or other effects, and which may mask true states of the on-die signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an integrated circuit die, including an on-die measurement circuit to measure an on-die signal relative to an off-die generated reference signal.

FIG. 2 is a block diagram of the die of FIG. 1, wherein the on-die measurement circuit includes is configured to generate an indication of whether a feature of the on-die signal is less-than or greater-than a corresponding feature of the off-die reference signal.

FIG. 3 is a block diagram of the die of FIG. 1, further including on-die circuitry from which the on-die signal may be measured.

FIG. 4 is a block diagram of the die of FIG. 1, wherein the on-die measurement circuit is configured to measure a plurality of on-die signals.

FIG. 5 is a block diagram of another IC die, including a plurality of on-die measurement circuits, each to measure a corresponding set of one or more on-die signals.

FIG. 6 is a flowchart of a method of measuring a signal on an integrated circuit die.

FIG. 7 is a flowchart of a method of measuring an analog voltage on an integrated circuit die.

FIG. 8 is a flowchart of a method of measuring a plurality of signals on an integrated circuit die.

FIG. 9 is a flowchart of a method of measuring plurality of sets of one or more signals on an integrated circuit die.

In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION

Disclosed herein are methods and systems to measure a signal on an integrated circuit die and to output an indication of the measure from the die.

FIG. 1 is a block diagram of an integrated circuit die 100, including an on-die measurement circuit 102 to measure an on-die signal 104 relative to an off-die generated reference signal 106, and to output an indication 108 of the measurement to an off-die accessible, electrically conductive pad 110.

Die 100 may include an externally accessible electrically conductive pad 112 to receive reference signal 106 from an off-die signal source 114.

Indication 108 may be monitored at off-die at pad 110 with electronic monitoring and/or test equipment, which may include one or more of an oscilloscope, a voltage sensor/meter, a current sensor/meter, and/or a test set.

On-die measurement circuit 102 may be utilized during testing and debugging of die 100. Alternatively, or additionally, measurement circuit 102 may be utilized during operation of die 100 to monitor performance.

On-die measurement circuit 102 may be configured to measure a voltage level of on-die signal 104 relative to a voltage level of off-die reference signal 106. On-die measurement circuit 102 is not, however, limited to measuring voltage.

On-die measurement circuit 102 may be configured to generate indication 108 as an indication of whether a measure of on-die signal 104 is less-than or greater-than a measure of off-die reference signal 106, such as disclosed below with reference to FIG. 2.

On-die implementation of measurement circuit 102 may help to protect on-die signal 104 from IR loading and/or capacitive effects that may otherwise be introduced by off-die measurement techniques.

On-die implementation of measurement circuit 102 may avoid buffers and/or driver circuits that may otherwise be used to drive on-die signal 104 to an externally accessible pad for off-die measurement.

On-die signal 104 may be tapped for measurement at a location that is physically proximate to a node of interest. This may help to protect on-die signal 104 from IR drop and/or capacitive effects.

For example, on-die measurement circuit 102 may be positioned physically proximate to the node of interest. Alternatively, or additionally, die 100 may further include an analog buffer to tap on-die signal 104 at a location proximate to the node of interest, and to provide a buffered version of on-die signal 104 to measurement circuit 102. The analog buffer may substantially isolate other circuitry that uses on-die signal 104, referred to herein as functional path circuitry, from potential noise and/or other potential effects related to measurement circuit 102. The analog buffer may include a unity-gain analog buffer (UGB), and may be implemented within measurement circuit 102.

On-die measurement circuit 102 may be configured to generate indication 108 from a voltage and/or current source other than on-die signal 104. This may help to protect on-die signal 104 from IR drops and/or capacitive effects.

On-die measurement circuit 102 may be configured to generate indication 108 as one of first and second voltage levels, such as to indicate whether a measure of on-die signal 104 is less-than or greater-than a measure of off-die reference signal 106. This may render indication 108 substantially insensitive to amplitudes of on-die signal 104 and off-die generated reference signal 106, and to potential drop between on-die measurement circuit 102 and pad 110.

On-die measurement circuit 102 may be further configured to generate indication 108 from a voltage source that is greater than a voltage of on-die signal 104, such as a system reference voltage, and to provide a voltage swing between the first and second voltage levels that is greater than the voltage of on-die signal 104.

On-die measurement circuit 102 may be useful to measure voltages during testing and/or debugging of an IC. For example, and without limitation, on-die measurement circuit 102 may be useful in debugging of input/output (I/O) circuits, such as to measure bandgap reference voltage levels, bias voltage levels, and/or other reference and/or control voltages. As another example, on-die measurement circuit 102 may be used to characterize circuits that generate reference and/or control voltages, such as voltage divider circuits and bias generation circuits. On-die measurement circuit 102 is not, however, limited to testing and debugging, and may be implemented to measure on-die signal 104 after die is deployed for operation.

On-die measurement circuit 102 may provide relatively accurate measurement of on-die signal 104 without subjecting on-die signal 106 to potential adverse effects of off-die measurement techniques.

FIG. 2 is a block diagram of die 100, wherein on-die measurement circuit 102 includes a comparator 202 to compare on-die signal 104 to off-die reference signal 106, and to generate indication 108 as an indication of whether a feature of on-die signal 104 is less-than or greater-than a corresponding feature of off-die reference signal 106.

Comparator 202 may be configured to continuously compare on-die signal 104 to off-die reference signal 106.

Off-die source 114 may be configured to vary off-die reference signal 106, and comparator 202 may be configured to change a state of indication 108 when a measure of off-die reference signal 106 exceeds a corresponding measure of on-die signal 104.

Comparator 202 may include a voltage comparator to compare voltage levels of on-die signal 104 and off-die reference signal 106, and may be configured to compare analog, or direct current voltage levels. Comparator 202 is not, however, limited to a voltage comparator.

Comparator 202 may be configured to compare direct current, or analog voltage levels of on-die signal 104 and off-die reference signal 106.

Off-die signal source 114 may be powered independently of die 100, and may include a relatively high-current-drive voltage source. This may help to overcome potential IR drop between source 114 and measurement circuit 102, which may help to ensure measurement accuracy. Off-die signal source 114 is not, however, limited to a voltage source.

Off-die signal source 114 may be programmable or otherwise configured to generate reference signal 106 as a series of changing reference voltage levels, which may include a sequence of incrementally increasing voltage steps, referred to herein as stepped voltage levels or a stepped voltage.

The sequence of stepped voltage levels may begin with a voltage level that is less than a voltage level of on-die signal 104, and may incrementally increase to a voltage level that is greater than that of on-die signal 104. Off-die Source 114 may be configured to incrementally increase the voltage level of off-die reference signal 106 to a system voltage level of die 100, or until the voltage level of off-die reference signal 106 exceeds the voltage level of on-die signal 104.

Comparator 202 may include n-type and/or p-type devices, which may include one or more n-type and/or p-type metal-oxide semiconductor field effect transistors (MOSFET). Selection of n-type and/or p-type devices may be based, at least in part, on relative signal levels encountered by on-die measurement circuit 102. For example, where a voltage of on-die signal 104 is relatively small compared to a system reference voltage level, p-type devices may be more suitable to measure on-die signal 104. Where a voltage of on-die signal 104 is relatively large compared to the system reference voltage level, p-type devices may be more suitable to measure on-die signal 104. Comparator may include multiple selectable comparators to compare for different voltage levels of on-die signal 104.

Comparator 202 may be further configured to generate indication 108 from a voltage signal other than on-die signal 104, such as a system reference voltage, and with a voltage swing defined by and/or substantially equal to the system reference voltage, such as disclosed below with reference to FIG. 3.

FIG. 3 is a block diagram of die 100, further including on-die circuit 302. On-die circuitry 302 may include one or more voltage dividers 304 to generate one or more reference voltages 306 from a system reference voltage Vcc 308. System reference voltage Vcc 308 may be received from an off-die source.

On-die circuitry 302 may include circuitry 310, which may include one or more of logic, input/output (I/O) circuitry, and/or signal processing circuitry, and which may receive one or more reference voltages 316 and/or system reference voltage Vcc 308.

On-die signal 104 may correspond to one or more signals within circuitry 302, and may include one or more reference voltages 306 and/or one or more signals within circuitry 310.

On-die measurement circuit 102 may be configured to generate indication 108 from system reference voltage Vcc 308, with a voltage swing substantially equal to system reference voltage Vcc 308. For example, where on-die measurement circuit 102 is configured to generate indication 108 as one of two voltage levels, such as disclosed above with reference to FIG. 2, on-die measurement circuit 102 may be further configured to generate the first and second voltage levels voltage levels with a voltage swing that is substantially equal to system reference voltage Vcc 308.

Die 100 may include one or more buffer or driver circuits to drive indication 108 to pad 110.

On-die measurement circuit 102 may configured to measure a plurality of on-die signals, such as disclosed below with reference to FIG. 4.

FIG. 4 is a block diagram of IC die 100, wherein on-die measurement circuit 102 includes measurement circuitry 402 and an input multiplexer 404 selectively provide a plurality of on-die signals 104-1 through 104-N to measurement circuitry 402 under control of a control signal 408. Control signal 408 may be received from on off die source, which may be controlled manually and/or programmably.

Measurement circuitry 406 may include a comparator, such as disclosed above with reference to FIG. 2, and may include circuitry 302 or portions thereof, such as disclosed above with reference to FIG. 3.

An IC die may include multiple on-die measurement circuits, such as disclosed below with reference to FIG. 5. Multiple on-die measurement circuits, or a portion thereof, may be configured similarly to one another. Alternatively, or additionally, multiple on-die measurement circuits, or a portion thereof, may be configured differently from one another.

FIG. 5 is a block diagram of an IC die 500, including a plurality of on-die measurement circuits 502, 504, 506, and 508.

On-die measurement circuits 502 and 504 are each illustrated to measure a plurality of corresponding on-die signals 510 and 512 relative to an off-die generated reference signal 514, and to generate corresponding indications 518 and 520, such as disclosed with respect to one or more examples herein.

Measurement circuit 502 includes measurement circuitry 522 and a multiplexer 524 to selectively provide on-die signals 510 to measurement circuitry 522.

Measurement circuit 504 includes measurement circuitry 526 and a multiplexer 528 to selectively provide on-die signals 512 to measurement circuit 526.

In the example of FIG. 5, multiplexers 524 and 528 are controlled by a shared input control signal 530, which may be generated off-die. Alternatively, multiplexers 524 and 528 may be controlled by separate input control signals.

IC 500 further includes an output multiplexer 532 to selectively output indications 518 and 520 to a shared pad 533 under control of an output control signal 534, which may be generated off-die.

An off-die system may be configured correlate multiplexed indications 518 and 520 at pad 533 with respective measurement circuits 502 and 504, based on input control signal 534, and to an on-die signal within on-die signals 510 and 512 based on input control signal 530.

Measurement circuit 506 is illustrated to measure a plurality of on-die signals 536 relative to an off-die reference signal 538, and to generate a measurement indication 540, such as disclosed above with reference to FIG. 4. Measurement circuit 506 includes measurement circuitry 542 and a multiplexer 544 to selectively provide on-die signals 536 to measurement circuitry 542 under control of an input control signal 544.

Measurement circuit 508 is illustrated to measure an on-die signal 546 relative to an off-die reference signal 547, and to generate a measurement indication 548, such as disclosed with respect to one or more examples herein.

Die 500 further includes circuitry 550, from which on-die signals 512, 512, 536, and 546 are received by measurement circuits 504, 504, 506, and 508. Circuitry 550 may include circuitry such as disclosed with respect to one or more examples herein.

On-die measurement circuits 504, 504, 506, and 508 may each be located physically proximate to portions of circuitry 550 from which corresponding on-die signals 512, 512, 536, and 546 are tapped for measurement. This may reduce or avoid IR drop between the tap locations and the measurement circuits.

Measurement indications 518, 520, 540, and 548 may be generated relative to a system reference voltage, such as disclosed above with reference to FIG. 3, and or may be buffered with one or more buffers 552, 554, 556, and 558, as illustrated in FIG. 5.

On or more of on-die measurement circuits 504, 504, 506, and 508 may include a comparator, such as disclosed above with reference to FIG. 3. On-die measurement circuits 504, 504, 506, and 508 are not, however, limited to comparators.

Methods of measuring a signal on an integrated circuit die are disclosed below with reference to FIGS. 6 through 9.

FIG. 6 is a flowchart of a method 600 of measuring a signal on an integrated circuit die.

At 602, an off-die generated reference signal is received at an integrated circuit die. The reference signal may include a series of increasing analog voltage steps, such as disclosed in one or more examples above.

At 604, an on-die signal is measured relative to the off-die generated reference signal, on the die. The measuring may include generating an indication of the measurement. The measuring may include measuring an analog voltage, such as disclosed below with reference to FIG. 7.

FIG. 7 is a flowchart of a method 700 of measuring an analog voltage of a signal on an integrated circuit die.

At 702, an off-die generated reference voltage is received at an integrated circuit die. The reference voltage may include a series of increasing analog voltage steps, such as disclosed in one or more examples above.

At 704, an analog voltage of an on-die signal is compared to analog reference voltage, on the die.

At 706, when the on-die signal voltage is greater than the reference voltage, an indication is set to a first voltage at 708. When the off-die reference voltage is greater than the on-die signal voltage, the indication is set to a second voltage at 710.

The measuring may be performed continuously as illustrated by arrows directed from 708 and 710 to 704. During continuous measuring, the analog reference voltage may increase incrementally, such as disclosed in one or more examples above, and the indication may change from the first voltage level to the second voltage level when the reference voltage exceeds the on-die signal voltage.

The indication may be provided to an off-die accessible pad of the IC, such as to permit monitoring of the indication.

FIG. 8 is a flowchart of a method 800 of measuring a plurality of signals on an integrated circuit die.

At 802, an off-die generated reference signal is received at an integrated circuit die, such as disclosed in one or more examples above.

At 804, one of a plurality of on-die signals is selected. The selecting may include multiplexing one of the plurality of on-die signals to a measurement circuit under control of a control signal. The control signal may be received from an off-die source.

At 806, the selected on-die signal is measured with reference to the off-die generated reference signal, such as disclosed in one or more examples above.

At 808, an indication of the measurement is generated, such as disclosed in one or more examples above.

FIG. 9 is a flowchart of a method 900 of measuring a plurality of sets of on-die signals with corresponding on-die measurement circuits.

At 902, an off-die generated reference signal is received at an integrated circuit die, such as disclosed in one or more examples above.

At 904, one of a plurality on-die signals is measured relative to the reference signal, by one of a plurality of on-die measurement circuits, such as disclosed in one or more examples above. The on-die signal may be selected from a plurality of on-die signals, such as disclosed above with reference to FIG. 8.

At 906, an indication of the measure is generated, such as disclosed in one or more examples above.

At 908, the measure is multiplexed to an off-die accessible pad of the die.

At 910, the measuring, generating, and multiplexing at 904, 906, and 908 may be performed continuously with respect to the on-die signal and the measurement circuit, such as to measure the on-die signal with respect to a series of increasing voltage steps of the reference signal.

The measuring, generating, and multiplexing at 904, 906, and 908 may be halted with respect to the on-die signal and the measurement circuit at 910, such as when a voltage of the reference signal exceeds a voltage of the on-die signal.

At 912, when another on-die signal is to be measured, processing returns to 902. At this point, the off-die generated reference signal may be reset to an initial value, such as an initial voltage, and the measuring, generating, and multiplexing at 904, 906, and 908 may be performed continuously for the other on-die signal until halted. The other signal may be measured with the same measurement circuit as a prior iteration or another measurement circuit.

The multiplexing at 908 may permit indications from the plurality of on-die measurement circuits to be output to a shared pin of the die.

Methods and systems are disclosed herein with the aid of functional building blocks illustrating the functions, features, and relationships thereof. At least some of the boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

While various embodiments are disclosed herein, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made therein without departing from the spirit and scope of the methods and systems disclosed herein. Thus, the breadth and scope of the claims should not be limited by any of the example embodiments disclosed herein. 

We claim:
 1. A processor comprising: a first pad; a second pad; a measurement circuit having: a first input node to receive a test signal; a second input node to receive a reference signal from the first pad; and an output node to provide an indication of a relation between the test signal and the reference signal to the second pad, wherein the measurement circuit is to protect the first input node from the second pad to preserve signal fidelity of the test signal.
 2. The processor of claim 1, wherein the test signal is to be provided from a circuit having a different power supply than the measurement circuit.
 3. The processor of claim 1, including a circuit to be tested (a test circuit) is to generate the test signal and is to operate on a first power supply.
 4. The processor of claim 3, wherein the measurement circuit has circuitry to operate at a second power supply higher than the first power supply.
 5. The processor of claim 4, wherein the indication signal is to be generated by a circuitry operating on the second power supply.
 6. The processor of claim 1 comprising a multiplexer having: a first input coupled to the output of the measurement circuit; a second input coupled to an output of another measurement circuit; and an output coupled to the second pad.
 7. The processor of claim 6, wherein the other measurement circuit has an input for receiving another test signal.
 8. The processor of claim 1, wherein the measurement circuit comprises a comparator having at least two inputs coupled to the first and second inputs respectively.
 9. The processor of claim 8, wherein the comparator comprises an output node for providing a digital signal.
 10. The processor of claim 8, wherein the comparator is to change state of its output when voltage of the test signal is higher than voltage of the reference signal.
 11. The processor of claim 1, wherein the reference signal is generated by an off-chip source.
 12. The processor of claim 6, wherein the off-chip source is to provide an adjustable voltage threshold as the reference signal.
 13. The processor of claim 1 comprising a circuit to provide an analog signal as the test signal.
 14. An integrated circuit apparatus, comprising: a circuit to be tested (test circuit), operating on a first power supply, to provide a test signal; a first pad; a second pad; and a measurement circuit having circuitry operating at a second power supply higher than the first power supply, the measurement circuit including: a first input node for receiving the test signal; a second input node for receiving a reference signal from the first pad; and an output node for providing an indication signal, indicating a relation between the test signal and the reference signal, to the second pad, wherein the indication signal is to be generated by the circuitry operating on the second power supply.
 15. The integrated circuit apparatus of claim 14, wherein the measurement circuit includes a comparator.
 16. The integrated circuit apparatus of claim 15, wherein the measurement circuit is one of a plurality of different measurement circuits whose outputs are selectably coupled together through one or more multiplexers to measure a selected one of a plurality of different test signals.
 17. The integrated circuit apparatus of claim 14, wherein the reference signal is generated by an off-chip source.
 18. The integrated circuit apparatus of claim 17, wherein the off-chip source is to provide an adjustable voltage threshold as the reference signal.
 19. A method comprising: receiving a test signal on a first input node; receiving, by a second input node, a reference signal from a first pad; providing, to an output node, an indication of a relation between the test signal and the reference signal to the second pad; and protecting the first input node from the second pad to preserve signal fidelity of the test signal.
 20. The method of claim 19, wherein the test signal is to be provided from a circuit having a different power supply than the measurement circuit. 